The present invention relates to a phase-locked loop. More particularly the present invention relates to a method and apparatus usable in an information recording and reproducing device for detecting a sampling phase of a signal read by a signal reproducing circuit in an optical recording and reproducing device.
In general, an information recording and reproducing device such as a hard disk is equipped with a phase-locked loop or device to generate a sampling clock synchronized with a signal read from a data recording medium. The phase-locked loop performs phase synchronization based on a synchronizing signal having a predetermined period prior to the commencement of a data reproducing operation and thereafter performs a phase follow-up operation for data reproduction. As one type of conventional apparatus phase-locked loop, there is known a phase-locked loop or device for detecting a phase difference from sampled data obtained by sampling a read signal so as to generate a sampling clock. This type of phase-locked loop requires an improvement in the accuracy of detecting the phase difference to stabilize a phase lock or to conduct synchronous operation. According to a phase-locked loop or device disclosed in Japanese Patent Application Laid-Open No. 1-143447, for example, there is disclosed apparatus wherein data is reliably judged by changing a decision level of sampled data on the basis of the past decision data thereby stably detecting a phase difference.
The above-described conventional phase-locked loop must allow for a reliable decision or determination of sampled data by enhancing the accuracy of detecting the phase difference and completing the decision of the sampled data. The accuracy of detection of the phase difference must be insured each time the sampling clock is input. Therefore, a data decision circuit employed using the above-described conventional phase-locked loop makes a data decision using a so-called feedback circuit for performing the present data decision in correspondence with the past decision result. However, the feedback circuit interferes with high-speed operation of the phase-locked loop as the sampling clock is speeded up, thereby making it difficult to operate the phase-locked loop at high speed.